1. Technical Field
The present invention relates to a charge transfer device.
2. Related Art
FIG. 10 is a schematic drawing showing a linear CCD (charge coupled device) image sensor of related art. A CCD image sensor 101 has photodiodes 110, a CCD register 120, and a transfer gate electrode 130. On one end of the CCD register 120, there are provided a charge detecting unit 40 and an output circuit 50. The transfer gate electrode 130 is provided between the photodiodes 110 and the COD register 120.
FIG. 11 is a plan view showing a region in the vicinity of the photodiodes, the transfer gate electrode and the CCD register in the CCD image sensor 101. The photodiodes 110 are isolated from each other by a device isolation region 114 formed of a P+-type diffusion layer.
The CCD register 120 contains four types of electrodes 121 to 124. The electrodes 121 are Φ1 storage electrodes formed of N-type polysilicon. The electrodes 122 are Φ1 barrier electrodes. The electrodes 123 are Φ2 storage electrodes formed of N-type polysilicon. The electrodes 124 are Φ2 barrier electrodes. These electrodes 121 to 124 are repetitively arranged in this order. The electrodes 121 to 124 are connected via contacts 125 to metal interconnects 126, 127, and are supplied with drive pulses Φ1 or Φ2. Assuming now pitch of unit cell in the direction of electron transfer as L, the configuration herein is such as making four electrodes 121 to 124 corresponded to L.
FIG. 13A and FIG. 13B are sectional views respectively taken along line H-H′ and line I-I′ in FIG. 11. In the surficial portion of a silicon substrate 111, there is a P-type well 112 formed on an N-type silicon substrate, and there is an N-type well 113 formed further in the surficial portion thereof. In the surficial portion of the P-type well 112, there are also a P+-type diffusion layer 114′ forming the device isolation region, an N-type diffusion layer 115 and a P+-type diffusion layer 116 forming the photodiodes 110, and N−-type diffusion layers 117, formed therein.
FIG. 14A and FIG. 14B are a timing chart of drive pulses shown in FIG. 11 and potential diagrams, respectively. By applying drive pulses Φ1 and Φ2, differed in the phase by 180° from each other, respectively to terminals Φ1, Φ2, potential at the portions under the individual electrodes varies, and electrons are serially transferred leftward in the drawing.
Similar technical art is disclosed in Japanese Laid-Open Patent Publication No. 2001-308313. Other technical arts are disclosed in Japanese Laid-Open Patent Publication Nos. 2004-22624, 2001-196572, and 2005-209879.
By the way, in order to realize lower power consumption of CCD image sensor, the present inventor has recognized that it is effective to lower the potential of the CCD section, and to lower NW (N well) concentration. However, lower NW concentration makes surface interference more likely to occur, raises a need of adjusting the potential of portions under the barrier electrode at a deeper level, and consequently results in a problem of reduction in maximum charge storage capacity of CCD.
FIG. 12 is a plan view of an output section 102 of a CCD image sensor 101. FIG. 13C is a sectional view taken along line J-J′ in FIG. 12. FIG. 18A is a timing chart of drive pulses, and FIG. 18B is a sectional view of the output section of the CCD register and a potential diagram. The signal charges transferred from the CCD register 120 are output to the floating diffusion layer 146 while placing output gate electrode 140 in between. The MOS transistor 143 and the load register 144 forms the amplifier of the source follower. And being output to the floating diffusion layer 146 the signal charges are output as the voltage signal to the output terminal 145 from the amplifier of the source follower. Afterward, the signal charges are drained to the resetting drain 142 while placing reset gate electrode 141 in between. Here, owing to be output the signal charges as the voltage signal by the source follower, the power supply voltage VDD of the source follower is larger than the reset voltage (the power supply voltage VRD). In addition, COD is a device sequentially transferring electric charge (electrons) from higher potential side to lower potential side, so that potential in the regions under the individual transfer electrodes should always be lower than the resetting potential (power source voltage VRD). The signal charges are output as the output voltage from the source follower. Owing to keep high gain of the source follower, the power supply voltage VDD of the source follower is larger than the reset voltage (the power supply voltage VRD). Accordingly, in order to realize lower power consumption of CCD image sensor it is effective to lower the resetting potential (the power source voltage VRD) if the power supply voltage VDD of the source follower is lowered for lowering the power consumption. For this reason, for the purpose of ensuring a desirable level of transfer efficiency, or a desirable level of electric field intensity causing transfer, even when the power source voltage VRD is lowered aiming at low-voltage operation, it is inevitably necessary to concomitantly lower potential in the region under the individual transfer electrodes of the CCD register. This may be realized by lowering the NW concentration, if clock pulses to be applied to the individual transfer electrodes are left unchanged.
FIG. 15A and FIG. 15B are drawings for explaining potential at a section under the CCD storage electrodes in FIG. 13B (a section taken along line K-K′). The solid line represents potential attained under the CCD storage electrodes, and the broken line represents potential attained under the CCD barrier electrodes. Electric charge is accumulated in the portion (hatched area) between the potential attained under the storage electrodes and the deepest potential attained under the barrier electrodes. As shown in FIG. 15A, potential under the barrier electrodes is set so as to prevent the electric charge (electrons) accumulated under the storage electrodes from being brought into contact with the surface of the silicon substrate. This state is referred to as “barrier limit”, and the maximum charge storage capacity in this state is referred to as “maximum charge storage capacity under barrier limit”.
As shown in FIG. 15B, when potential barrier Δφh_st1, equivalent to potential difference between the deepest portion of channel under the CCD storage electrodes and surface potential, is smaller than potential difference Δφba2 between the deepest potential under the storage electrodes and the deepest potential under the barrier electrodes, the accumulated electric charge reaches the interface between the N-type well and the oxide film. This state is referred to as “surface limit”, and the maximum charge storage capacity in this state is referred to as “maximum charge storage capacity under surface limit”. In the surface limit state, electric charge is trapped at the interface between the N-type well and the oxide film in the process of charge transfer, so-called surface interference may occur, and this results in transfer failure. Therefore, in CCD registers, it is generally necessary to adjust the potential in the region under the barrier electrodes so as to establish the state of barrier limit.
FIG. 17A is a drawing showing NW concentration dependence of the potential under the storage electrodes. FIG. 17B is a drawing showing NW concentration dependence of the charge storage capacity. Lowering in the NW concentration makes the channel potential φnw lower (shallower), and makes position of the channel closer to the surface side, thereby potential barrier Δφph is lowered, and the surface limit becomes more likely to be achieved. As a consequence, the maximum charge storage capacity of CCD reduces as the NW concentration lowers.
FIG. 16A is a drawing showing dependence of potential under the storage electrodes on electrode potential (Vg). FIG. 16B is a drawing showing Vg dependence of accumulated charge. Higher Vg raises (deepens) the channel potential φnw, and makes position of the channel closer to the surface side, so that the potential barrier Δφh is lowered, making the surface limit more likely to be achieved. As a consequence, the maximum charge storage capacity of CCD decreases as the Vg elevates.
Accordingly, lower NW concentration makes the surface interference more likely to occur even when the clock voltage in the process of transfer is left unchanged, so that potential under the barrier electrodes need be adjusted to a deeper level, but this consequently reduces the maximum charge storage capacity of CCD.